1. FIELD OF THE INVENTION
The present invention relates to a glitch detection circuit and method for detecting a glitch included in an input signal to an oscilloscope or the like.
2. DESCRIPTION OF THE PRIOR ART
A glitch refers to a perturbation of the pulse waveform of relative short duration and of uncertain origin, which unexpectedly occurs during an acquisition interval. Here, the acquisition interval, which is longer than or equal to a sampling interval, refers to an interval between the two adjacent acquisition points at which sampled values of the input signal are acquired for recording.
In general, a conventional glitch detection circuit cannot convert a glitch occurring during the acquisition interval from an analog signal to a digital signal as long as the glitch occurs and disappears within the acquisition interval, and hence such a glitch cannot be detected by the conventional glitch detection circuit.
Such a glitch is a noise consisting of components above the Nyquist frequency, according to the quantization theory, and can be suitably eliminated by a filter in normal cases. However, it is often necessary to detect the presence and magnitude of such a glitch occurring during the acquisition interval in order to distinguish an accidental abnormality from a normal steady phenomenon.
To accomplish this, maximum and minimum amplitudes of a signal waveform inputted during the acquisition interval must be detected and recorded. U.S. Pat. No. 4,271,486 (Dagostino, et al., "Waveform storage system", Tektronix, Inc., Published Jun. 2, 1981) teaches an example to achieve such operation as follows: first, it converts an input signal from an analog signal to a digital signal by using an analog-to-digital circuit at a sampling rate higher than the acquisition rate at which the input signal is measured; second, it detects the maximum and minimum values of the digital data produced from the analog-to-digital circuit during each acquisition interval; and finally it stores the maximum and minimum values in a memory so as to detect a glitch.
FIG. 1 is a block diagram showing a conventional circuit used for detecting the maximum and minimum values to detect a glitch. The operation of this circuit will be described.
An analog-to-digital converter 41 carries out an A/D conversion at a sampling interval shorter than an acquisition interval which is determined in accordance with a time axis range of a measurement. Recording of the acquired data to memories 49 and 55 is performed at the acquisition interval which is assumed to be m times the length of the sampling interval of the analog-to-digital converter 41. In other words, the maximum and minimum values among every m pieces of digital data are recorded to the memories 49 and 55.
The digital data produced from the analog-to-digital converter 41 are transferred to maximum value holding flip-flops 44, a maximum value comparing circuit 46, minimum value holding flip-flips 50 and a minimum value comparing circuit 52.
Detection of the maximum value is carried out as follows. First, the maximum value holding flip-flops 44 hold first digital data. Second, the maximum value comparing circuit 46 compares a second data newly produced from the analog-to-digital converter 41 with the first data held in the maximum value holding flip-flops 44, and waits for the next (third) data performing nothing when the second data is less than the first data held in the maximum value holding flip-flops 44. In contrast, when the second data is greater than the first data held in the flip-flops 44, the maximum value comparing circuit 46 applies a signal to a maximum value holding signal generating circuit 47, which generates a holding signal 48. The maximum value holding flip-flops 44 read the second digital data and hold it in response to the holding signal 48, and wait for the next (third) digital data.
When the third digital data is produced from the analog-to-digital converter 41, the foregoing cycle is repeated until m pieces of digital data are processed, that is, until one acquisition interval is completed.
When the cycle with regard to the latest digital data of the acquisition interval is completed, the data held in the maximum value holding flip-flops 44 is the maximum value among the m pieces of data, and this data is recorded in the acquisition memory 49 as a maximum value. Upon completion of the processing of m pieces of the data, the maximum value holding signal generating circuit 47 produces the holding signal 48 to hold the next digital data from the analog-to-digital converter 41, i.e., the first data of the next m pieces of data from the analog-to-digital converter 41, and repeats the above processing.
Similar cycles are carried out to detect minimum values. The minimum value comparing circuit 52 compares the preceding minimum value held in the minimum value holding flip-flops 50 with new digital data produced from the analog-to-digital circuit 41. The data greater than the preceding minimum value is ignored, whereas the data less than the preceding minimum value is read into the minimum value holding flip-flips 50 as a new minimum value. Upon processing m pieces of data, the minimum value among the m pieces of data is recorded in an acquisition memory 55 as in the processing of maximum values. After that, the first data of the next m pieces of data is held, thus repeating the foregoing cycle.
The above-described conventional glitch detection circuit detects a glitch by judging the maximum and minimum values among the digital data obtained over the acquisition interval determined in accordance with a time axis range selected, and by recording the maximum and minimum values.
The conventional circuit, however, includes a feedback loop consisting of the comparing circuit, holding signal generating circuit and maximum or minimum value holding flip-flops because the conventional technique holds, in the process of detecting the maximum and minimum values, these maximum and minimum values based on the compared result between the preceding maximum or minimum value and the new data supplied from the analog-to-digital converter 41. As a result, the total sum of transfer delay times of these circuits determines the signal processing time, which hinders signal processing at a high sampling rate.
For example, the maximum operation speed of the conventional circuit can be evaluated in terms of the sampling frequency with regard to the conventional circuit arranged as shown in FIG. 2 by using high speed logic elements whose speed is approximately equal to that of AS-TTL (Advanced Schottky Transistor-Transistor Logic) elements.
Let us assume that the conventional circuit is composed of the following elements: the maximum value holding flip-flops 44 and the minimum value holding flip-flops 50 are 74AS574, the maximum value comparing circuit 46 and the minimum value comparing circuit 52 are 74AS885, and the holding signal generating circuits 47 and 53 are 74AS153. In this case, the delay time of each element is as follows: the time required to produce a result by comparing the new digital data with the preceding data, that is, the delay of 74AS885 is 5.5 nanoseconds; the time required to generate the holding signal in response to the output of the comparing circuit, that is, the delay of 74AS153 is 5 nanoseconds; and the time required from the production of the holding pulse to the establishment of the new data, that is, the delay time of 74AS574 is 6 nanoseconds (the sum total so far is 16.5 nanoseconds). In addition, when latch circuits of 74AS574 (not shown in FIG. 2) are used to load the maximum and minimum data into the memories 49 and 52, another 2 nanoseconds are required, thereby resulting in the total transfer delay time of 18.5 nanoseconds when AS-TTLs are used to arrange the circuit. In other words, the upper limit of the sampling frequency of the analog-to-digital converter becomes about 54 MHz. Taking into account the margin for positive operation, the upper limit of the sampling frequency must be further reduced.
In order to operate the conventional circuit at a higher sampling frequency, higher speed logic elements are required. For example, to operate it reliably at a 100 MHz sampling frequency, the circuit must be composed of logic elements having a speed of 100K series ECL logic elements.
However, logic circuits whose clock speed is on the order to 100 MHz are commonly composed of TTL logic elements. In such a case, mixing the ECL logic elements with the TTL logic elements presents disadvantages in terms of cost, power consumption, and packaging area. For this reason, even in a waveform storage device including an analog-to-digital converter with a high sampling frequency, the sampling frequency must sometimes be reduced when the glitch detection function is in operation.